A low-power multilevel CMOS classifier circuit

İnsanların günlük yaşamında belirli bir sesi, görüntüyü veya analog bir veriyi tanımak için kullandıkları kuralları tanımlamak oldukça karmaşık bir dizi işlem gerektirmektedir ve hatta bu kuralları tanımlamak bazen mümkün olamamaktadır. Oysa pratikte karşılaşılan örüntü tanıma olaylarını, yazılım ve donanım tabanlı tanıma uygulamalarında belirli kriterlere oturtmak mümkündür. Sınıflandırma yöntemleri ilk olarak örüntü sınıflandırma adı altında görülmeye başlanmış ve ilk algoritmalarda basit yapılar ele alınmıştır; ilk gerçeklenen yapıda en yakın komşu yakınsaması kullanılmıştır. Sınıflandırma işlemi, benzer özellik taşıyan objelerin başka farklı özellikte olanlardan ayırt edilmesi şeklinde tanımlanabilir ve otomatik hedef belirleme, yapay zekâ, yapay sinir ağları, analog-sayısal dönüştürücüler, kuantalama, tıbbi tanı, istatistik gibi çeşitli alanlarda kullanılır. Dolaysıyla da, günümüzde, gerek gerçek dünyada gerekse sayısal dünyada verilerin sınıflandırılması büyük önem taşımaktadır. Bugüne kadar sınıflandırma işlemi genellikle çeşitli algoritmalar yardımıyla yazılımsal olarak yapılmaktaydı, oysa birçok uygulamada, sınıflandırma işlemini daha hızlı ve gerçek zamanda yapmak gerektiğinden bu algoritmaların donanımsal olarak gerçeklenmeleri çok daha yararlı olmaktadır. Ayrıca günümüzde portatif cihazların da artmasından dolayı donanımsal olarak gerçeklenecek cihazlarda da güç tüketimi büyük önem kazanmıştır. Dolayısıyla sınıflandırıcı devrelerin de bu ihtiyaçları karşılayacak şekilde tasarlanması gerekmektedir. Bu makalede akım-modlu düşük güçte çalışan bir sınıflandırıcı devresi sunulmaktadır. Önerilen sınıflandırıcı devresi, temel bir bloktan yararlanmaktadır; bu temel bloklar kullanılarak daha gelişmiş sınıflandırıcı yapılarının gerçekleştirilebileceği gösterilmiştir. Önerilen devrenin benzetimleri için 0.35 μm AMS CMOS teknoloji parametreleri kullanılmıştır. Ayrıca çekirdek devre adı verilen temel bloğun, tek boyutlu ve iki boyutlu sınıflandırıcı yapılarının benzetim sonuçları verilmiştir.In the everyday life of humans, to define the rules used to recognize a certain sound, image or an analog data necessitates a sequence of complex processes which sometimes becomes impossible to accomplish. However, to develop well defined software and hardware based criteria in the application of pattern recognition problems, is possible. The aim of classification can be defined as to assign an unknown object to a class containing similar objects (or to distinguish objects having the same properties from those not possessing). Classification is especially important in the real world applications or in the digital world. Basic classification methods using nearest neighbourhood algorithm have first been seen in early sixties under the subject tile" pattern recognition." Classification is used in a huge variety of applications such as automatic target identification, artificial neural networks, artificial intelligence, template matching, pattern recognition, analog to digital converters, quantization, medical diagnosis, statistics etc. Therefore nowadays, be it in the real or digital world, data classification is becoming increasingly important. But until recently, major work on classification was on developing algorithms used in software packages whereas, in many applications it is becoming more and more important to classify data much faster and in real time, entailing the need for hardware realization of these algorithms. Software approaches are not practical for real time applications, the processing is computationally very expensive, consuming a lot of Central Processing Unit (CPU) time when implemented as software running on general purpose computers. So in literature hardware implementation of classifier topologies become necessary. Also in literature hardware realized classifiers which are designed to work in low power operation; moreover some of these hardware classifiers do not have custom tunability. So they can only be used for a specific application. The recent developments in electronics technology has created a perfect medium for the hardware realization of classifier structures which, in turn, will render many classifier application prospects feasible in real time. This paper targets the design and application to real world problems of tunable, low power new classifier circuits using CMOS technology. So, a low-power CMOS implementation of a multi-input data classifier with several output levels is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. An architecture is developed comprising a threshold circuit based on CMOS transistors operating in subthreshold region. To this purpose a one dimensional classifier, called core circuit is proposed. The core circuit also works as a one-dimensional classifier. As this circuit is designed to operate in currentmode the input and the output data is provided to the core circuit with currents. So by interconnecting several core circuits and adding the output currents a multi output classifier can be obtained. Also, combining several core circuits in groups in such a way that each group has identical input current (different from the others), a multi-dimensional, multi-level output classifier can be obtained. Also, numerous efforts in balancing the trade off between power consumption, area and speed have resulted in an acceptable performance. On the other hand, the rapid increasing use of battery operated portable equipment in application areas such as telecommunications and medical electronics increases the importance of low-power and small sized VLSI circuits' technologies. One solution to achieve lowpower and acceptable performance is to operate the transistors in the subthreshold region. The CMOS transistors working in subthreshold region are suitable only for specific applications which need, not very high performance, but low power consumption. The primary aim of this paper is to develop a low power classifier circuit with n inputs and externally tunable decision regions with different output amplitude for each region. Due to the subthreshold operation of the transistors in the proposed core circuit, very low power consumption becomes possible. The proposed core circuit is constructed with two threshold and a subtractor circuit. The SPICE simulation of the threshold circuit, core circuit, one dimensional and two dimensional classifier circuits are given. Using 0.35 μm parameters of AMS CMOS technology, SPICE simulations are performed and a low-power, custom tunable classifier circuit is realized. Because of the parallel processing characteristic of the circuit, it is well suited for real-world applications

CMOS realization of a quantized-output classifier circuit

In this paper a CMOS implementation of a multi-input data classifier with several output levels and a different architecture is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. The classifier circuit’s new architecture consists of the interconnections of core cells each possessing a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using 0.35µm TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results

High swing CMOS realization for third generation current conveyor (CCIII)

In this paper a new CMOS realization for third generation current conveyor (CCIII) is proposed. The proposed circuit provides high swing range at terminals X and Y. The circuit has low input impedances at terminals X and Y and high output impedance at terminals Z+ and Z-. The circuit has 180MHz -3dB cutoff frequency in voltage follower mode. SPICE simulation results using MIETEC 1.2 CMOS process model are given

ASD: çok amaçlı ayarlanabilir sınıflandırıcı devreler

Göknar, İzzet Cem (Dogus Author) -- Minaei, Shahram (Dogus Author) -- Yıldız, Merih (Dogus Author)Çalışmada, ayarlanabilir sınıflandırıcı devreleri ve uygulama alanları incelenmiştir. AMS 0.35 μm CMOS prosesi ile, tasarlanan sınıflandırıcı bir tümdevrenin üretimi de yapılmıştır. Bu sınıflandırıcı devresinin kontrol parametrelerinin bulunmasını sağlayan öğrenme algoritmaları çeşitli uygulamalar için geliştirilmiştir. Sınıflandırma işlemleri geliştirilen algoritmalar ve üretilen devre ile İris ve Haberman veri kümelerine uygulanarak sonuçların uyum içinde olduğu gösterilmiştir.TÜBİTA

The effect of aerobic exercise program on pulmonary function and cardiorespiratory capacity in obese women

Objective: To examine the effects of a six-month aerobic exercise program on pulmonary function and cardiorespiratory capacity in obese women. Materials and Methods: A total of 50 subjects - 25 obese women who neither did regular exercise nor applied a special diet program, and 25 healthy controls - were included in the study. Body mass index (BMI), maximum oxygen consumption (VO2max) and pulmonary function tests (PFT) values were measured as evaluation parameters in both groups. Obese women were enrolled to a supervised hospital-based bicycle aerobic exercise program for six months at an individualized target heart rate range (50-85% of heart reserve), with an increasing frequency and duration. Evaluation parameters were reevaluated after the exercise program and were compared with the pre-exercise values. Results: VO2max, forced vital capacity (FVC), forced expiratory volume at first second (FEV1), FEV1/FVC, and maximum mid-expiratory flow rate (FEF25-75) were significantly lower in obese women (p<0.05). There was a statistically significant decrease at BMI and statistically significant increase at VO2max, FEV1, FEV1/FVC, and FEF25-75 among obese women after completing the 6-month exercise program. Conclusion: It was shown that obese women had lower cardiopulmonary capacity and PFTs when compared to non-obese ones and, aerobic exercise could improve cardiopulmonary capacity and PFTs in obese women. © Turkish Journal of Physical Medicine and Rehabilitation, Published by Galenos Publishing

Autologous Stem Cell Transplantation in Multiple Myeloma Patients Over 60 Years Old

The incidence of Multiple myeloma (MM) increases with age; two-thirds of the patients are older than 65 years. Induction treatment, including new agents such as thalidomide, bortezomib, and lenalidomide followed by a conditioning regimen and upfront autologous stem cell transplantation (ASCT), has been accepted the standard treatment approach for newly diagnosed fit MM patients. We aimed to search the real-life data, the efficacy and safety of upfront ASCT following induction in patients with MM over 60 years old retrospectively. The data of MM patients who were ≥60 years old during autologous stem cell transplantation and treated at our center between 2010 and 2018 retrospectively analyzed. The study results were 63 patients included at the age of ≥ 60 years who underwent upfront ASCT. Median PFS was 15.5±2.6 months, and the median overall survival (OS) was 28.15±5 months. According to age groups, median PFS was 12±2.3 months in the 60-64 age group, 18.4±6 months in the 65-69 age group, and 26±15 months in the ≥70 age group. Median OS was 26.5±6.1 months in the 60-64 age group, 39.66±8.9 months in the 65-69 age group, and 18 months in the ≥70 age group. A significant relationship between the quantity of infused CD34+ stem cells and PFS and OS (p:0.05 and

Early Relapse After Autologous Stem Cell Transplantation in Multiple Myeloma is Still Prognostic in The Era of Novel Agents

Significant improvements in the prognosis of Multiple Myeloma(MM) have recently observed in the era of novel agents. Induction treatment, including new agents followed by conditioning regimen and upfront autologous stem cell transplantation(ASCT), has been accepted as the standard treatment approach for newly diagnosed eligible MM patients. Despite novel agents, upfront ASCT is still superior to conventional chemotherapy alone. Previous studies revealed that the duration between ASCT and relapse had predicted overall survival(OS), and meantime, it was widely used to determine the potential benefit from a second ASCT. However, the majority of the data collected reflects the treatment modalities before novel agents. In this study, we aimed to investigate the impact of post-transplantation early relapse(ER) on survival in the era of novel agents. The results of 155 MM patients that underwent ASCT at our center between January 2010 and May 2018 were analyzed retrospectively. The median follow-up duration was 20 months in the ER group, 27 months in the non-ER group, and 24 months in all patients. 33.3% of patients in the ER group and 71.4% of patients in the non-ER group were alive at the time of analysis. Median OS was 20.77±3.66 months in the ER group and 40.89±4.21 months in the non-ER group. We found a statistically significant relationship between the ER and the poor OS (p

Does blood type have an effect on the course of COVID-19?

Introduction Predictive parameters that can affect the course of this infection have been the main topic of research since the beginning of the COVID-19 (Coronavirus disease 2019) pandemic. Since the discovery of blood groups, the effect of these on infectious diseases has always been of interest. Objectives To analyze the effect of ABO blood group on mortality, hospitalization duration and hematological and cytokine storm parameters in patients with COVID-19. Patients and methods: This retrospective study was conducted on 140 patients diagnosed with COVID-19. Demographic characteristics, laboratory parameters including ABO blood group, complete blood count (CBC) parameters, biochemical tests, cytokine storm parameters, duration of hospitalization, and final status (discharge or death) were recorded. Results: The 140 patients included in the analysis comprised 72 (51.4%) males and 68 (48.6%) females with a mean age of 66.3±14.0 years. . Age and gender, hospitalization duration and mortality rates were similar in all blood group types. Only D-dimer levels were found to be higher in blood group A compared with other blood groups. Conclusion: Although no difference in mortality was determined between groups, the D-dimer level was statistically significantly higher in COVID-19 patients with A blood group. Larger studies are needed to reflect D-dimer levels on the clinical course of infection, and thus on daily practice

New Possibilities In Tunable Cmos Classifier Circuits

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu çalışmada, ayarlanabilir sınıflandırıcı devreleri ve uygulama alanları incelenmiştir. Sınıflandırma işlemi, benzer özellik taşıyan objelerin farklı özellikte olanlardan ayırt edilmesi şeklinde tanımlanabilir ve otomatik hedef belirleme, yapay zekâ, yapay sinir ağları, analog-sayısal dönüştürücüler, tıbbi tanı, kuantalama, görüntü işleme, istatistik gibi konularda kullanım alanı bulur. Diğer yandan, gerek gerçek dünyada gerekse sayısal dünyada, verilerin sınıflandırılması büyük önem taşımaktadır. Sınıflandırma yöntemleri ilk olarak 1960’lı yıllarda örüntü sınıflandırma adı altında görülmeye başlanmış ve ilişkin algoritmalarda basit yapılar ele alınmıştır; ilk gerçeklenen yapıda en yakın komşu yakınsaması kullanılmıştır. Bugüne kadar sınıflandırma işlemi, çeşitli algoritmalar yardımıyla genellikle yazılımsal olarak yapılmıştır. Oysaki gerçek zamanda çalışma gerektiren bazı uygulamalarda, sınıflandırma işleminin donanımsal olarak da gerçeklenmesi önem kazanmaktadır. Bu amaçla, çalışmanın donanımsal gerçeklemeyle ilgili kısmında, önce çekirdek devre diye adlandırılan temel bir yapı tasarlanmış ve bu çekirdek devrelerden oluşan çok girişli-çok çıkışlı bir sınıflandırıcı mimarisi geliştirilmiştir. Bu sınıflandırıcı mimarisi ile sınıflandırılabilen ve sınıflandırılamayan veri kümeleri incelenmiş, sınıflandırılamayan veri kümelerinin ayırt edilebilmesi için çekirdek devre yapıları ile kullanılabilecek Çarpan Devre yapısı gerçekleştirilmiştir. Dolayısıyla gerek sadece çekirdek devre yapıları, gerekse çarpan devre yapıları ile beraber kullanılarak veri kümelerinin uygun kontrol parametreleri ile sınıflandırılabileceği gösterilmiştir. Bu kontrol parametrelerinin bulunmasını sağlayan eğitim algoritmaları da incelenmiştir. Sonuç olarak bu çalışmada, sınıflandırma işlemini donanımsal yapılar ile gerçekleştirebilecek, ayarlanabilir, eğitilebilen yeni sınıflandırıcı devreleri tasarlanmış, sağladıkları yeni olanakların gerçek dünyada bulunan ve de önemli olan uygulamalarda incelenmesi ile elde edilen sonuçlar verilmiş ve sınıflandırma konusundaki etkinlikleri ortaya konulmuştur.In this thesis, new possibilities in CMOS classifier circuits and their applications are investigated. Classifier circuits can find applications in various fields of applied science such as pattern recognition, artificial intelligence, neural networks, analog digital converters, quantizers and statistics. Therefore, classification is especially important in the real world applications or in the digital world. Firstly, basic classification methods using the nearest neighbourhood algorithm have been seen in 1960 as pattern recognition. Nowadays classification is generally achieved with the help of some algorithms aided with computer programs. However, hardware implementation of classifier circuits are important for the some applications that require real-time processing. For that reason, in this thesis firstly hardware implementation of a basic classification unit called core cell is presented. A multiple-input and multiple-output classification topology is constructed with these core cells. The data sets that can be classified or non-classified with that multiple-input and multiple-output classifier circuits have been investigated. A Scaler Circuit has been realized with core cells and used to classify data sets. As a result it is shown that the data sets, with only core cells or together with scaler circuits, can be classified with the appropriate control parameters. Learning algorithms have been investigated, developed and applied to obtain these control parameters. To conclude, in this thesis custom tunable CMOS classifier circuits have been designed, tested and applied. The test applications have been chosen from real world problems and the results have verified the effective performance of the classifier topologies and circuits.DoktoraPh

Sinusoidal Oscillator Design with Modified Current-Feedback Operational Amplifier

Bu çalışmada yeni bir aktif eleman olan iyileştirilmiş aktif geri beslemeli (MCFOA) blok devresi yardımıyla farklı osilatör topolojileri gerçekleştirilmiştir. Bu osilastör yapıları gerçekleştirilirken sadece bir adet MCFOA yapısı ve en fazla beş adet pasif eleman kullanılmıştır. Gerçekleştirilen osilatör yapılarının osilasyon kriterleri ve osilasyon frekanslarıdetaylı olarak incelenmiştir. Ayrıca MCFOA yapısındaki akım ve gerilim izleme hatalarından kaynaklanan idealsizlik etkileride ayrıca incelenmiştir.Simülasyonlar SPICE programı yardımıyla yapılmış ve 0.35?m TSMC CMOS teknoloji parametreleri kullanılmıştır. Ayrıca kullanılan devrede besleme gerilimi olarak 1.65 V alınmıştır. Gerçekleştirilen devrelerde osilasyon kriterlerinin osilasyon frekansı etkilemeyeck şekilde olmasına da dikkat edilerek tasarımlar gerçekleştirilmiştir. Simülasyon sonuçları teorik sonuçlar ile karşılaştırılmış ve makalede verilmiştir.In this study, different oscillator topologies have been realized with the help of a new active element, Modified Current-Feedback Operational Amplifier (MCFOA). Only one MCFOA element and a maximum number of five passive elements were used during the design of the oscillator circuits. The oscillation criteria and oscillation frequencies of the oscillator structures have been examined in detail.In addition, the non-ideality effects of MCFOA block, due to the current and voltage tracking errors, were also examined. The simulations were performed with SPICE program and 0.35?m TSMC CMOS technology parameters were used. The supply voltages are chosen as 1.65 V.It is ensured that the oscillation condition criteria in the circuits doesnot affect the oscillation frequency.Simulation results are compared with theoretical results and presented in paper